/*
 * Copyright (c) 2009-2010 HIT Microelectronic Center
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *
 * Authors: Gou Pengfei
 *
 * Date: Aug. 2010
 *
 */

#ifndef __CPU_EDGE_BASE_ATOMIC_INST_HH__
#define __CPU_EDGE_BASE_ATOMIC_INST_HH__

#include <bitset>
#include <list>
#include <deque>
#include <string>

#include "arch/faults.hh"
#include "base/fast_alloc.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "cpu/edge/exetrace.hh"
#include "cpu/edge/atomic/atomic_block.hh"
#include "cpu/inst_seq.hh"
#include "cpu/op_class.hh"
#include "cpu/edge/static_inst.hh"
#include "mem/packet.hh"
#include "sim/system.hh"
#include "sim/tlb.hh"

/**
 * @file
 * Defines a EDGE dynamic instruction context. 
 * This is really a simple class for atomicEdgeCPU
 */

// Forward declaration.
class EDGEStaticInstPtr;

template <class Impl>
class BaseAtomicEdgeDynInst : public FastAlloc, public RefCounted
{
  public:
    // Typedef for the CPU.
    typedef typename Impl::CPUType ImplCPU;
    typedef typename ImplCPU::ImplState ImplState;
    typedef typename Impl::EdgeBlockPtr EdgeBlockPtr;

    // Logical register index type.
    typedef TheISA::RegIndex RegIndex;
    // Integer register type.
    typedef TheISA::IntReg IntReg;
    // Floating point register type.
    typedef TheISA::FloatReg FloatReg;

    // The DynInstPtr type.
    typedef typename Impl::DynInstPtr DynInstPtr;
    
    typedef typename std::deque<DynInstPtr>::iterator QueueIt;

    enum {
        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
        MaxInstDestRegs = TheISA::MaxInstDestRegs,      /// Max dest regs
    };

    /** The EDGEStaticInst used by this BaseAtomicEdgeDynInst. */
    EDGEStaticInstPtr staticInst;

    ////////////////////////////////////////////
    //
    // INSTRUCTION EXECUTION
    //
    ////////////////////////////////////////////
    /** InstRecord that tracks this instructions. */
    Trace::EdgeInstRecord *traceData;

    /**
     * Does a read to a given address.
     * @param addr The address to read.
     * @param data The read's data is written into this parameter.
     * @param flags The request's flags.
     * @return Returns any fault due to the read.
     */
    template <class T>
    Fault read(Addr addr, T &data, unsigned flags);

    /**
     * Does a write to a given address.
     * @param data The data to be written.
     * @param addr The address to write to.
     * @param flags The request's flags.
     * @param res The result of the write (for load locked/store conditionals).
     * @return Returns any fault due to the write.
     */
    template <class T>
    Fault write(T data, Addr addr, unsigned flags,
                        uint64_t *res);

    template<class T>
    Fault effAddrComp(T data, Addr addr, unsigned flags,
        uint64_t *res);

    /** @todo: Consider making this private. */
  public:
    /** The sequence number of the instruction. */
    InstSeqNum seqNum;

    enum Status {
        IqEntry,                 /// Instruction is in the IQ
        RobEntry,                /// Instruction is in the ROB
        LsqEntry,                /// Instruction is in the LSQ
        Completed,               /// Instruction has completed
        BlockCompleted,          /// Block of this instruction has completed
        ResultReady,             /// Instruction has its result
        CanIssue,                /// Instruction can issue and execute
        Issued,                  /// Instruction has issued
        Executed,                /// Instruction has executed
        CanCommit,               /// Instruction can commit
        AtCommit,                /// Instruction has reached commit
        Committed,               /// Instruction has committed
        Squashed,                /// Instruction is squashed
        SquashedInIQ,            /// Instruction is squashed in the IQ
        SquashedInLSQ,           /// Instruction is squashed in the LSQ
        SquashedInROB,           /// Instruction is squashed in the ROB
        RecoverInst,             /// Is a recover instruction
        BlockingInst,            /// Is a blocking instruction
        ThreadsyncWait,          /// Is a thread synchronization instruction
        SerializeBefore,         /// Needs to serialize on
                                 /// instructions ahead of it
        SerializeAfter,          /// Needs to serialize instructions behind it
        SerializeHandled,        /// Serialization has been handled
        PredMatched,              /// Predication matched
        Nullified,                        /// This inst has received nullify token

        NumStatus
    };

    /** The status of this BaseAtomicEdgeDynInst.  Several bits can be set. */
    std::bitset<NumStatus> status;

    /** The thread this instruction is from. */
    ThreadID threadNumber;

    /** data address space ID, for loads & stores. */
    short asid;

    /** Pointer to the Impl's CPU object. */
    ImplCPU *cpu;

    /** Pointer to the thread state. */
    ImplState *thread;

    /** The kind of fault this instruction has generated. */
    Fault fault;

    /** Pointer to the data for the memory access. */
    uint8_t *memData;

    /** The effective virtual address (lds & stores only). */
    Addr effAddr;

    /** Whether the effective address has been calculated. */
    bool eaCalcDone;

    /** The size of mem access. Currently only used for dump block outputs. */
    int memAccSize;

    /** Is the effective virtual address valid. */
    bool effAddrValid;

    /** The effective physical address. */
    Addr physEffAddr;

    /** The memory request flags (from translation). */
    unsigned memReqFlags;

    /** The memory access request generated by a store inst.*/
    RequestPtr memReq;

    /** PC of this instruction. */
    Addr PC;

  protected:

     /** Edge inst block class pointer this inst belongs to. */
    EdgeBlockPtr instBlock;

    /** Next non-speculative PC.  It is not filled in at fetch, but rather
     *  once the target of the branch is truly known (either decode or
     *  execute).
     */
    Addr nextPC;

    /** Next non-speculative NPC. Target PC for Mips or Sparc. */
    Addr nextNPC;

    /** Predicted next PC. */
    Addr predPC;

    /** Predicted next block PC. */
    Addr predBlockPC;

    /** Predicted next NPC. */
    Addr predNPC;

    /** If this is a branch that was predicted taken */
    bool predTaken;

    /** Block status of this dyn inst*/
    TheISA::BlockStatus blockStatus;

  public:

#ifdef DEBUG
    void dumpSNList();
#endif

  protected:

    /** Physical register index of the destination registers of this
     *  instruction.
     */
    PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];

    /** Physical register index of the source registers of this
     *  instruction.
     */
    PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];

  public:

    /**
     * This method will be used to set a proper dest reg idx
     * when mapping inst blocks.
     */
    void mapDestReg(int idx,
                       PhysRegIndex mapped_dest )
    {
        _destRegIdx[idx] = mapped_dest;
    }

    /** Get the mapped dest reg idx. */
    PhysRegIndex getMappedDestReg( int idx ) const
    {
        return _destRegIdx[idx];
    }

    /** change renameSrcReg to mapSrcReg.
     * This method will be used to set a proper src reg idx
     * when mapping inst blocks.
     */
    void mapSrcReg(int idx, PhysRegIndex mapped_src)
    {
        _srcRegIdx[idx] = mapped_src;
    }

    /** Get mapped src reg idx. */
    PhysRegIndex getMappedSrcReg ( int idx ) const
    {
        return _srcRegIdx[idx];
    }

    /** BaseAtomicEdgeDynInst constructor given a binary instruction.
     *  @param staticInst A EDGEStaticInstPtr to the underlying instruction.
     *  @param PC The PC of the instruction.
     *  @param pred_PC The predicted next PC.
     *  @param pred_NPC The predicted next NPC.
     *  @param seq_num The sequence number of the instruction.
     *  @param cpu Pointer to the instruction's CPU.
     */
    BaseAtomicEdgeDynInst(EDGEStaticInstPtr staticInst, Addr PC, Addr NPC,
            Addr pred_PC, Addr pred_NPC,
            InstSeqNum seq_num, ImplCPU *cpu, TheISA::BlockStatus blockstatus);

    /** BaseAtomicEdgeDynInst constructor given a binary instruction.
     *  @param inst The binary instruction.
     *  @param PC The PC of the instruction.
     *  @param pred_PC The predicted next PC.
     *  @param pred_NPC The predicted next NPC.
     *  @param seq_num The sequence number of the instruction.
     *  @param cpu Pointer to the instruction's CPU.
     */
    BaseAtomicEdgeDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC,
            Addr pred_PC, Addr pred_NPC, 
            InstSeqNum seq_num, ImplCPU *cpu, TheISA::BlockStatus blockstatus);

    /** BaseAtomicEdgeDynInst constructor given a EDGEStaticInst pointer.
     *  @param _staticInst The EDGEStaticInst for this BaseAtomicEdgeDynInst.
     */
    //BaseAtomicEdgeDynInst(EDGEStaticInstPtr &_staticInst);

    /** BaseAtomicEdgeDynInst destructor. */
    ~BaseAtomicEdgeDynInst();

  private:
    /** Function to initialize variables in the constructors. */
    void initVars();

  public:
    /** Dumps out contents of this BaseAtomicEdgeDynInst. */
    void dump();

    /** Dumps out contents of this BaseAtomicEdgeDynInst into given string. */
    void dump(std::string &outstring);

    /** Read this CPU's ID. */
    int cpuId() { return cpu->cpuId(); }

    /** Read this context's system-wide ID **/
    int contextId() { return thread->contextId(); }

    /** Returns the fault type. */
    Fault getFault() { return fault; }

    /** Set fault method allowing set fault externally. */
    void setFault(Fault fault_to_set ) { fault = fault_to_set; }

    /** Returns the next PC.  This could be the speculative next PC if it is
     *  called prior to the actual branch target being calculated.
     */
    Addr readNextPC() { return nextPC; }

    /** Return the next block PC. */
    Addr getNextBlockPC() const { return instBlock->getBranchTarget(); }

    /** Return the block pc of this inst*/
    Addr getBlockPC() { return instBlock->getStartPC(); }

    /** Return the block pointer of this inst. */
    EdgeBlockPtr getBlockPtr() const { return instBlock;}


    /** Returns the next NPC.  This could be the speculative next NPC if it is
     *  called prior to the actual branch target being calculated.
     */
    Addr readNextNPC()
    {
        return nextPC + sizeof(TheISA::MachInst);
    }

    /** Set the predicted target of this current instruction. */
    void setPredTarg(Addr predicted_PC, Addr predicted_NPC)
    {
        predPC = predicted_PC;
        predNPC = predicted_NPC;
    }

    /** Set the predicted target of this inst block. */
    void setPredBlockTarg( Addr predicted_block_pc )
    {
        predBlockPC = predicted_block_pc;
    }

    /** Returns the predicted PC immediately after the branch. */
    Addr readPredPC() { return predPC; }

    /** Returns the predicted block PC. */
    Addr readPredBlockPC() const { return predBlockPC;}

    /** Returns the predicted PC two instructions after the branch */
    Addr readPredNPC() { return predNPC; }

    /** Returns whether the instruction was predicted taken or not. */
    bool readPredTaken()
    {
        return predTaken;
    }

    void setPredTaken(bool predicted_taken)
    {
        predTaken = predicted_taken;
    }

    /** Returns whether the instruction mispredicted. */
    bool mispredicted()
    {
        return readPredPC() != readNextPC() ||
            readPredNPC() != readNextNPC();
    }

    //
    //  Instruction types.  Forward checks to EDGEStaticInst object.
    //
    bool isGRegWR() const { return staticInst->isGRegWR(); }
    bool isMove() const { return staticInst->isMove(); }
    bool isTest() const {return staticInst->isTest();}
    bool isConst() const {return staticInst->isConst();}
    bool isNullify() const {return staticInst->isNullify();}
    bool isNop()          const { return staticInst->isNop(); }
    bool isRead() const { return staticInst->isRead(); }
    bool isWrite() const { return staticInst->isWrite(); }
    bool isMemRef()       const { return staticInst->isMemRef(); }
    bool isLoad()         const { return staticInst->isLoad(); }
    bool isStore()        const { return staticInst->isStore(); }
    bool isStoreConditional() const
    { return staticInst->isStoreConditional(); }
    bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
    bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
    bool isCopy()         const { return staticInst->isCopy(); }
    bool isInteger()      const { return staticInst->isInteger(); }
    bool isFloating()     const { return staticInst->isFloating(); }
    bool isControl()      const { return staticInst->isControl(); }
    bool isCall()         const { return staticInst->isCall(); }
    bool isReturn()       const { return staticInst->isReturn(); }
    bool isDirectCtrl()   const { return staticInst->isDirectCtrl(); }
    bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
    bool isCondCtrl()     const { return staticInst->isCondCtrl(); }
    bool isUncondCtrl()   const { return staticInst->isUncondCtrl(); }
    bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
    bool isThreadSync()   const { return staticInst->isThreadSync(); }
    bool isSerializing()  const { return staticInst->isSerializing(); }
    bool isSerializeBefore() const
    { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
    bool isSerializeAfter() const
    { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
    bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
    bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
    bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
    bool isQuiesce() const { return staticInst->isQuiesce(); }
    bool isIprAccess() const { return staticInst->isIprAccess(); }
    bool isUnverifiable() const { return staticInst->isUnverifiable(); }
    bool isSyscall() const { return staticInst->isSyscall(); }
    bool isMacroop() const { return staticInst->isMacroop(); }
    bool isMicroop() const { return staticInst->isMicroop(); }
    bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
    bool isLastMicroop() const { return staticInst->isLastMicroop(); }
    bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
    bool isMicroBranch() const { return staticInst->isMicroBranch(); }

    /** Temporarily sets this instruction as a serialize before instruction. */
    void setSerializeBefore() { status.set(SerializeBefore); }

    /** Clears the serializeBefore part of this instruction. */
    void clearSerializeBefore() { status.reset(SerializeBefore); }

    /** Checks if this serializeBefore is only temporarily set. */
    bool isTempSerializeBefore() { return status[SerializeBefore]; }

    /** Temporarily sets this instruction as a serialize after instruction. */
    void setSerializeAfter() { status.set(SerializeAfter); }

    /** Clears the serializeAfter part of this instruction.*/
    void clearSerializeAfter() { status.reset(SerializeAfter); }

    /** Checks if this serializeAfter is only temporarily set. */
    bool isTempSerializeAfter() { return status[SerializeAfter]; }

    /** Sets the serialization part of this instruction as handled. */
    void setSerializeHandled() { status.set(SerializeHandled); }

    /** Checks if the serialization part of this instruction has been
     *  handled.  This does not apply to the temporary serializing
     *  state; it only applies to this instruction's own permanent
     *  serializing state.
     */
    bool isSerializeHandled() { return status[SerializeHandled]; }

    bool isPredMatched() const { return status[PredMatched]; }
    void setPredMatched() { status.set(PredMatched); }
    bool isNullified() const { return status[Nullified]; }
    bool isBlockSpeculative() { return instBlock->isSpeculative();}

    void setNullified() { status.set(Nullified); }

    /** Returns the opclass of this instruction. */
    OpClass opClass() const { return staticInst->opClass(); }

    /** Returns the branch target address. */
    Addr branchTarget() const { return staticInst->branchTarget(PC); }

    /** Returns the instruction block branch target address. */
    Addr blockBranchTarget() const { return instBlock->getBranchTarget(); }

    /** Returns the number of source registers. */
    int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }

    /** Returns the number of destination registers. */
    int8_t numDestRegs() const { return staticInst->numDestRegs(); }

    /** Returns the logical register index of the i'th destination register. */
    RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }

    /** Returns the logical register index of the i'th source register. */
    RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }

    /** Sets the block of this instruction has completed. */
    void setBlockCompleted() { status.set(BlockCompleted);}

    /** Returns whether or not the block of this instruction is completed. */
    bool isBlockCompleted() { return status[BlockCompleted]; }

    /** Sets this instruction as completed. */
    void setCompleted() { status.set(Completed); }

    /** Returns whether or not this instruction is completed. */
    bool isCompleted() const { return status[Completed]; }

    /** Sets this instruction as ready to issue. */
    void setCanIssue() { status.set(CanIssue); }

    /** Returns whether or not this instruction is ready to issue. */
    bool readyToIssue() const { return status[CanIssue]; }

    /** Clears this instruction being able to issue. */
    void clearCanIssue() { status.reset(CanIssue); }

    /** Sets this instruction as issued from the IQ. */
    void setIssued() { status.set(Issued); }

    /** Returns whether or not this instruction has issued. */
    bool isIssued() const { return status[Issued]; }

    /** Clears this instruction as being issued. */
    void clearIssued() { status.reset(Issued); }

    /** Sets this instruction as executed. */
    void setExecuted()
    { 
        status.set(Executed);

        // Increment executed inst counter in its inst block
        instBlock->executedInsts++;
    }

    /** Returns whether or not this instruction has executed. */
    bool isExecuted() const { return status[Executed]; }

    /** Sets this instruction as ready to commit. */
    void setCanCommit() { status.set(CanCommit); }

    /** Clears this instruction as being ready to commit. */
    void clearCanCommit() { status.reset(CanCommit); }

    /** Returns whether or not this instruction is ready to commit. */
    bool readyToCommit() const { return status[CanCommit]; }

    void setAtCommit() { status.set(AtCommit); }

    bool isAtCommit() { return status[AtCommit]; }

    /** Sets this instruction as committed. */
    void setCommitted() { status.set(Committed); }

    /** Returns whether or not this instruction is committed. */
    bool isCommitted() const { return status[Committed]; }

    /** Sets this instruction as squashed. */
    void setSquashed() { status.set(Squashed); }

    /** Returns whether or not this instruction is squashed. */
    bool isSquashed() const { return status[Squashed]; }

    //Instruction Queue Entry
    //-----------------------
    /** Sets this instruction as a entry the IQ. */
    void setInIQ() { status.set(IqEntry); }

    /** Sets this instruction as a entry the IQ. */
    void clearInIQ() { status.reset(IqEntry); }

    /** Returns whether or not this instruction has issued. */
    bool isInIQ() const { return status[IqEntry]; }

    /** Sets this instruction as squashed in the IQ. */
    void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}

    /** Returns whether or not this instruction is squashed in the IQ. */
    bool isSquashedInIQ() const { return status[SquashedInIQ]; }


    //Load / Store Queue Functions
    //-----------------------
    /** Sets this instruction as a entry the LSQ. */
    void setInLSQ() { status.set(LsqEntry); }

    /** Sets this instruction as a entry the LSQ. */
    void removeInLSQ() { status.reset(LsqEntry); }

    /** Returns whether or not this instruction is in the LSQ. */
    bool isInLSQ() const { return status[LsqEntry]; }

    /** Sets this instruction as squashed in the LSQ. */
    void setSquashedInLSQ() { status.set(SquashedInLSQ);}

    /** Returns whether or not this instruction is squashed in the LSQ. */
    bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }


    //Reorder Buffer Functions
    //-----------------------
    /** Sets this instruction as a entry the ROB. */
    void setInROB() { status.set(RobEntry); }

    /** Sets this instruction as a entry the ROB. */
    void clearInROB() { status.reset(RobEntry); }

    /** Returns whether or not this instruction is in the ROB. */
    bool isInROB() const { return status[RobEntry]; }

    /** Sets this instruction as squashed in the ROB. */
    void setSquashedInROB() { status.set(SquashedInROB); }

    /** Returns whether or not this instruction is squashed in the ROB. */
    bool isSquashedInROB() const { return status[SquashedInROB]; }

    /** Mem ref inst would like to get the last store in LSID sequence. */
    TheISA::LsID getLastStore() {
        assert(isMemRef());
        return instBlock->getLastStore(staticInst->getLSID());
    }

    /** Read the PC of this instruction. */
    const Addr readPC() const { return PC; }

    /** Set the next PC of this instruction (its actual target). */
    void setNextPC(Addr val)
    {
        nextPC = val;
    }

    /** Set the block PC of this inst*/
    void setBlockPC(Addr val)
    {
        instBlock->setStartPC(val);
    }

    /** Set the PC of the next inst block. */
    void setNextBlockPC( Addr val )
    {
        instBlock->setBranchTarget(val);
    }

    /** Sets the block pointer of this inst. */
    void setBlockPtr(EdgeBlockPtr block_ptr) { instBlock = block_ptr; }

    /** Sets the ASID. */
    void setASID(short addr_space_id) { asid = addr_space_id; }

    /** Sets the thread id. */
    void setTid(ThreadID tid) { threadNumber = tid; }

    /** Sets the pointer to the thread state. */
    void setThreadState(ImplState *state) { thread = state; }

    /** Returns the thread context. */
    ThreadContext *tcBase() { return thread->getTC(); }

  private:

    /** Is this instruction's memory access uncacheable. */
    bool isUncacheable;

    /** Has this instruction generated a memory request. */
    bool reqMade;

  public:
    /** Sets the effective address. */
    void setEA(Addr &ea)
    { 
        effAddr = ea; 
        eaCalcDone = true;
        effAddrValid = true;
    }

    /** Returns the effective address. */
    //const Addr &getEA() const { return instEffAddr; }
    const Addr &getEA() const { return effAddr; }

    /** Returns whether or not the eff. addr. calculation has been completed. */
    bool doneEACalc() { return eaCalcDone; }

    /** Returns whether or not the eff. addr. source registers are ready. */
    bool eaSrcsReady();

    /** Whether or not the memory operation is done. */
    bool memOpDone;

    /** Is this instruction's memory access uncacheable. */
    bool uncacheable() { return isUncacheable; }

    /** Has this instruction generated a memory request. */
    bool hasRequest() { return reqMade; }

  public:

    /** Iterator pointing to this BaseAtomicEdgeDynInst in the queue of IQ. */
    QueueIt instQueueIt;

    /** Returns iterator to this instruction in IQ. */
    QueueIt &getInstQueueIt() { return instQueueIt; }

    /** Sets iterator for this instruction in the IQ. */
    void setInstQueueIt(QueueIt queueit) { instQueueIt = queueit; }
};

template<class Impl>
template<class T>
inline Fault
BaseAtomicEdgeDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
{
    reqMade = true;
    Request *req = new Request(asid, addr, sizeof(T), flags, this->PC,
                               thread->contextId(), threadNumber);

    fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read);

    if (req->isUncacheable())
        isUncacheable = true;

    if (fault == NoFault) {
        effAddr = req->getVaddr();
        effAddrValid = true;
        physEffAddr = req->getPaddr();
        memReqFlags = req->getFlags();
        memAccSize = req->getSize();

        DPRINTF(AtomicEdgeCPU, "Vaddr: %#x, Paddr:%#x.\n", effAddr, physEffAddr);

        fault = cpu->read(req, data, staticInst->getLSID());

        // Pointer to the reqeust is stored in 'memReq'
        // so that it can be destroyed once this inst class
        // goes out of its scope.
        memReq = req;

    } else {
        // Return a fixed value to keep simulation deterministic even
        // along misspeculated paths.
        data = (T)-1;

        // Commit will have to clean up whatever happened.  Set this
        // instruction as executed.
        this->setExecuted();
        delete req;
    }

    if (traceData) {
        traceData->setAddr(addr);
        traceData->setData(data);
    }

    return fault;
}

template<class Impl>
template<class T>
inline Fault
BaseAtomicEdgeDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
    assert((!effAddrValid) || 
        (effAddrValid && (addr == effAddr) && 
        (data == *((T*)memData))));

    // If memReq has been generated, 
    // we do the real access to memory.
    // If not, we calculate the effective
    // address, set up the request, and
    // set flags properly.
    // This is used in AtomicEdgeCPU to
    // split the EA generating process
    // and the real access to memory.
    if (memReq) {

        if (fault == NoFault) {          
            fault = cpu->write(memReq, data, staticInst->getLSID());
        } 
    } else {
        fault = effAddrComp(data, addr, flags, res);
    }

    return fault;
}

template<class Impl>
template<class T>
inline Fault
BaseAtomicEdgeDynInst<Impl>::effAddrComp(T data, Addr addr, unsigned flags, uint64_t *res)
{
    if (traceData) {
        traceData->setAddr(addr);
        traceData->setData(data);
    }

    reqMade = true;
    Request *req = new Request(asid, addr, sizeof(T), flags, this->PC,
                               thread->contextId(), threadNumber);
                               
    fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write);

    if (req->isUncacheable())
        isUncacheable = true;

            
    if (fault == NoFault) {
    
        effAddr = req->getVaddr(); 
        eaCalcDone = true;
        effAddrValid = true;
        physEffAddr = req->getPaddr();
        memReqFlags = req->getFlags();
        memAccSize = req->getSize();
        
        DPRINTF(AtomicEdgeCPU, "Vaddr: %#x, Paddr:%#x.\n", effAddr, physEffAddr);
        
        // Set data to store
        T gData = htog(data);
        
        assert(memData==NULL);
        
        memData = new uint8_t[64];
        memcpy(memData,&gData,memAccSize);
        
        if (req->isCondSwap()) {
            assert(res);
            req->setExtraData(*res);
        }

        // Store this req pointer so that it
        // can be used when write func is called.
        memReq = req;
        
    } else {
        delete req;
    }

    return fault;
}

#endif // __CPU_EDGE_BASE_ATOMIC_INST_HH__
